The schedule of the HT 2011 course can be found at HT11 Schedules (click on IL2217)
Introduction to general system design flow and implementation techniques. Introduction to hardware description languages (HDLs). VHDL. The synthesisable subset. Alternative HDLs. System modelling using VHDL. Design and analysis of combinational and sequential components. Implementation architectures. Synthesis towards FPGAs. Asynchronous vs. Synchronous Finite State Machines (FSMs). Micro controllers/processors and data busses.
Written exam (TEN1 3hp), passed laboration course (LAB1 4.5hp) with 4 laborations.
The course is examined continously. Each passed laboration also has the
function of a minor examination which gives bonus points for the written exam.
The laborations contributes with the folloing points to the exam (total 10 points=1 grade step):
One written exam. The exam is divided into two parts, part B (theory) and part A (coding/structures). The theory part (part B) will be based on any theory and material given during lab and lectures and the coding part (part A) will be a mixture of VHDL coding and understanding the structures the code represent.
A student is guaranteed to pass the exam if the student has at least five (20) points on part A and at least five (20) on part B and a total on the exam of at least 50 points. A student that has passed all laborations before the first exam has automatically 10 points on the exam and hence needs only to get the 20 points each on part A and B, to pass the exam and achieve the grade E.
| Course part | Lecture | Topic | Notes |
|---|---|---|---|
| Introduction to VHDL | |||
| F1 (JÖ) | Why VHDL? (2/page pdf) (6/page pdf) | ||
| F2 (JÖ) | Modeling Styles (2/page pdf) (6/page pdf) | ||
| F3 (JÖ) | Datatypes & Conversion functions (2/page pdf) (6/page pdf) | ||
| Ö1 (JÖ) | VHDL Hierarchy: Entity, Architecture and Testbenches | ||
| L1 | Combinational Components (two occasions) | ||
| Introduction to Synthesis & FSMs | |||
| F4 (JÖ) | Latches, Flip-Flops, Resolved types and data buses (2/page pdf) (6/page pdf) | ||
| L2 | Flip-flops, Resolution functions and Data buses | ||
| F5 (JÖ) | FSM Modelling and Synthesis (2/page pdf) (6/page pdf) | ||
| F6 (JÖ) | Introduction to RTL Synthesis - The synthesizable VHDL subset (2/page pdf) (6/page pdf) | ||
| Ö2 (JÖ) | Synchronous Finite State Machines (FSMs) | ||
| L3 | Counters & Finite State Machines (FSMs) | ||
| Modelling Complex Designs | |||
| F7 (JÖ) | FSMDs - FSMs with a Datapath (2/page pdf) (6/page pdf) | ||
| F8 (JÖ) | Modelling Complex Systems (2/page pdf) (6/page pdf) | ||
| Ö3 (JÖ) | The Synthesizable Subset | ||
| L4 (two occasions) | The Micro Controller | ||
| F9 (JÖ) | Asynchronous State Machines (2/page pdf) (6/page pdf) | ||
| Ö4 (JÖ) | Asynchronous State Machines | ||
| Other HDL-standards | |||
| F10 (??) | Introduction to Verilog (2/page pdf) (6/page pdf) | ||
| F11 (AH?) | Introduction to System C and Transaction Level Modelling (TLM) (2/page pdf) (6/page pdf) | ||
| E X A M I N A T I O N | |||
| Ö5 (JÖ) | Solving selected exam problems
Exam 20071026 Solutions to Exam 20071026 Re-Exam 20080117 Solutions to Re-Exam 20080117 |
||
| Remaining Labs? | Last chance to examine remaining labs before exam | ||
| Exam | NB! Don't forget to register for the exam!!!
(Register Now!) |
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| Re-exam |
Don't forget to fill in the course evaluation in Daisy!!!